Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/alu.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/alu_ctrl.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/control.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/dp_memory.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/ex_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/forwarding_unit.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/hazard_unit.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/id_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/if_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/mem_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/mips_system.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/pipeline.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/regfile.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/wb_stage.v" into library work