Running: fuse.exe -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "D:/Xilinux/Lab3/Lab3_1/testbench_isim_beh.exe" -prj "D:/Xilinux/Lab3/Lab3_1/testbench_beh.prj" "work.testbench" "work.glbl" ISim P.20131013 (signature 0x7708f090) Number of CPUs detected in this system: 4 Turning on mult-threading, number of parallel sub-compilation jobs: 8 Determining compilation order of HDL files Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/regfile.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/control.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/alu_ctrl.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/alu.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/wb_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/mem_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/if_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/id_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/hazard_unit.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/forwarding_unit.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/ex_stage.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/pipeline.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/dp_memory.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/mips_system.v" into library work Analyzing Verilog file "D:/Xilinux/Lab3/Lab3_1/testbench.v" into library work Analyzing Verilog file "D:/Xilinux/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work Starting static elaboration Completed static elaboration Compiling module if_stage Compiling module hazard_unit Compiling module base_forwarding_unit Compiling module forwarding_unit Compiling module regfile Compiling module control Compiling module id_stage Compiling module alu_ctrl Compiling module alu Compiling module ex_stage Compiling module mem_stage Compiling module wb_stage Compiling module pipeline Compiling module dp_memory Compiling module mips_system Compiling module testbench Compiling module glbl Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 17 Verilog Units Built simulation executable D:/Xilinux/Lab3/Lab3_1/testbench_isim_beh.exe Fuse Memory Usage: 27140 KB Fuse CPU Usage: 718 ms