Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to D:/Xilinux/Lab4/UART/xst/projnav.tmp


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.54 secs
 
--> Parameter xsthdpdir set to D:/Xilinux/Lab4/UART/xst


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.54 secs
 
--> WARNING:Xst:3164 - Option "-debug" found multiple times in the command line. Only the first occurence is considered.

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "fifo.v" in library work
Module <fifo> compiled