Running: D:\Xilinux\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o D:/Xilinux/Lab4/UART/test_uart_controller_isim_beh.exe -prj D:/Xilinux/Lab4/UART/test_uart_controller_beh.prj work.test_uart_controller work.glbl ISim P.20131013 (signature 0x7708f090) Number of CPUs detected in this system: 4 Turning on mult-threading, number of parallel sub-compilation jobs: 8 Determining compilation order of HDL files Analyzing Verilog file "D:/Xilinux/Lab4/UART/uart_tx.v" into library work Analyzing Verilog file "D:/Xilinux/Lab4/UART/uart_rx.v" into library work Analyzing Verilog file "D:/Xilinux/Lab4/UART/uart.v" into library work Analyzing Verilog file "D:/Xilinux/Lab4/UART/fifo.v" into library work Analyzing Verilog file "D:/Xilinux/Lab4/UART/uart_controller.v" into library work Analyzing Verilog file "D:/Xilinux/Lab4/UART/test_uart_controller.v" into library work Analyzing Verilog file "D:/Xilinux/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work Starting static elaboration WARNING:HDLCompiler:329 - "D:/Xilinux/Lab4/UART/uart_controller.v" Line 60: Target of concurrent assignment or output port connection should be a net type. WARNING:HDLCompiler:329 - "D:/Xilinux/Lab4/UART/uart_controller.v" Line 61: Target of concurrent assignment or output port connection should be a net type. WARNING:HDLCompiler:329 - "D:/Xilinux/Lab4/UART/uart_controller.v" Line 65: Target of concurrent assignment or output port connection should be a net type. Completed static elaboration Compiling module uart_tx Compiling module uart_rx Compiling module uart Compiling module fifo Compiling module uart_controller Compiling module test_uart_controller Compiling module glbl Time Resolution for simulation is 1ps. Compiled 7 Verilog Units Built simulation executable D:/Xilinux/Lab4/UART/test_uart_controller_isim_beh.exe Fuse Memory Usage: 26792 KB Fuse CPU Usage: 671 ms