`timescale 1ns / 1ps

module test_uart;

	// Inputs
	reg clk;
	reg rstn;
	reg rx;
	reg read_en;
	reg [7:0] write_data;
	reg write_en;

	// Outputs
	wire tx_ready;
	wire data_ready;
	wire [7:0] read_data;
	wire tx;

	// Instantiate the Unit Under Test (UUT)
	uart uut (
		.clk(clk), 
		.rstn(rstn), 
		.rx(rx), 
		.read_en(read_en), 
		.read_data(read_data), 
		.write_data(write_data), 
		.write_en(write_en), 
		.tx(tx),
		.tx_ready(tx_ready),
		.data_ready(data_ready)
	);

	initial begin
		// Initialize Inputs
		rstn = 0;
		rx = 0;
		read_en = 0;
		write_data = 0;
		write_en = 0;

		// Wait 100 ns for global reset to finish
		#100;
      rstn = 1;
		rx = 1;
      write_data = 8'b1010_1010;
		#50
		write_en = 1;
		#1800
		write_en = 0;
		
		#50
		#30
		read_en = 1;
		#200 rx = 1;
		#160 rx = 0;
                #160 rx = 1; //0101_0111
                #160 rx = 1;
                #160 rx = 1;
                #160 rx = 0;
                #160 rx = 1;
                #160 rx = 0;
                #160 rx = 1;
                #160 rx = 0;
					 #500 rx = 1;

	end
	
	initial begin
      clk = 0;
		forever #10 clk = ~clk;
   end
      
endmodule