`timescale 1ns / 1ps

module test_uart_controller;

	// Inputs
	reg clk;
	reg rst;
	reg addr;
	reg w_en;
	reg r_en;
	reg [31:0] w_data;
	reg rx;

	// Outputs
	wire [31:0] r_data;
	wire interrupt;
	wire tx;

	// Instantiate the Unit Under Test (UUT)
	uart_controller uut (
		.clk(clk), 
		.rst(rst), 
		.addr(addr), 
		.w_en(w_en), 
		.r_en(r_en), 
		.w_data(w_data), 
		.r_data(r_data), 
		.interrupt(interrupt), 
		.rx(rx), 
		.tx(tx)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		addr = 0;
		w_en = 0;
		r_en = 0;
		w_data = 0;
		rx = 0;

		// Wait 100 ns for global reset to finish
		#100;
      rst = 0;
		
		#20
		@(posedge clk);
		
		w_data = 987654;
		w_en = 1;
		@(posedge clk);
      w_en = 0;
		
		w_data = 4;
		w_en = 1;
		@(posedge clk);
      w_en = 0;
	
		@(posedge clk);
		@(posedge clk);
		w_data = 5;
		w_en = 1;
		@(posedge clk);
      w_en = 0;
		
		w_data = 8;
		w_en = 1;
		@(posedge clk);
      w_en = 0;
		
		@(posedge clk);
		w_en = 0;
		
		w_data = 55;
		w_en = 1;
		@(posedge clk);
      w_en = 0;
		
	end
	
	initial begin
      clk = 0;
		forever #10 clk = ~clk;
   end
endmodule