`timescale 1ns / 1ps

module test_uart_rx;

	// Inputs
	reg clk;
	reg rx;
	reg rstn;
	reg read_en;

	// Outputs
	wire [7:0] data;
	wire data_ready;

	// Instantiate the Unit Under Test (UUT)
	uart_rx uut (
		.clk(clk), 
		.rstn(rstn),
		.rx(rx), 
		.read_en(read_en),
		.data(data), 
		.data_ready(data_ready)
	);

	initial begin
		// Initialize Inputs
		rx = 1;
		rstn = 0;
		read_en = 0;

		// Wait 100 ns for global reset to finish
		#100;
		rstn = 1;
		#30
		read_en = 1;
		#200 rx = 1;
		#160 rx = 0;
                #160 rx = 1; //0101_0111
                #160 rx = 1;
                #160 rx = 1;
                #160 rx = 0;
                #160 rx = 1;
                #160 rx = 0;
                #160 rx = 1;
                #160 rx = 0;
					 #160 rx = 1;
					 //read_en = 0;
					 //#200
					 //read_en = 1;
					 rx = 1;
				    #300
					 #160 rx = 0;
					 
                #160 rx = 1;//0111_0101
                #160 rx = 0;
                #160 rx = 1;
                #160 rx = 0;
                #160 rx = 1;
                #160 rx = 1;
                #160 rx = 1;
                #160 rx = 0;
					 #160 rx = 1;
					 //read_en = 0;
					 //#200
					 //read_en = 1;

	end
	
	initial
                #10000 $finish;

	initial begin
      clk = 0;
		forever #10 clk = ~clk;
   end
      
endmodule