`timescale 1ns / 1ps

module test_uart_tx;

	// Inputs
	reg clk;
	reg [7:0] data;
	reg start;
	reg rstn;

	// Outputs
	wire tx;
	wire ready;

	// Instantiate the Unit Under Test (UUT)
	uart_tx uut (
		.clk(clk), 
		.rstn(rstn),
		.data(data), 
		.start(start), 
		.tx(tx), 
		.ready(ready)
	);

	initial begin
		// Initialize Inputs
		data = 0;
		start = 0;
		rstn = 0;

		// Wait 100 ns for global reset to finish
		#100;
		rstn = 1;
      data = 8'b1010_1010;
		start = 1;

	end

	initial begin
      clk = 0;
		forever #10 clk = ~clk;
   end
      
endmodule