Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to D:/Xilinux/Lab4/UART/xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.31 secs
 
--> Parameter xsthdpdir set to D:/Xilinux/Lab4/UART/xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.31 secs
 
--> WARNING:Xst:3164 - Option "-debug" found multiple times in the command line. Only the first occurence is considered.

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "uart_tx.v" in library work
Compiling verilog file "uart_rx.v" in library work
Module <uart_tx> compiled
Compiling verilog file "uart.v" in library work
Module <uart_rx> compiled
Module <uart> compiled
No errors in compilation
Analysis of file <"uart.prj"> succeeded.
 


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.39 secs
 
--> 

Total memory usage is 201356 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)