`timescale 1ns / 1ps
module uart(
//Common
input   wire                    clk,
input   wire 						  rstn,
//RX
input   wire                    rx,
input	  wire						  read_en,
output  wire     [7:0]          read_data,
output  wire						  data_ready,

//TX
input   wire    [7:0]   write_data,
input   wire            write_en,
output  wire            tx,
output  wire				tx_ready
);

	uart_tx u_tx (
		.clk(clk), 
		.rstn(rstn),
		.data(write_data), 
		.start(write_en), 
		.tx(tx), 
		.ready(tx_ready)
	);
	
	uart_rx u_rx (
		.clk(clk), 
		.rstn(rstn),
		.rx(rx), 
		.data(read_data), 
		.data_ready(data_ready),
		.read_en(read_en)
	);


endmodule