`timescale 1ns / 1ps

`define BUF_WIDTH 10 

module uart_controller(
	input 					clk,
	input 					rst,
	input		wire			addr,
	input		wire			w_en,
	input		wire			r_en,
	input		wire[31:0]	w_data,
	output	wire[31:0]	r_data,
	output	wire			interrupt,
	
	input		wire			rx,
	output	wire			tx
    );
//commmon


//read_buffer
wire	[31:0]		rb_buf_in;
wire	[31:0]		rb_buf_out;
wire				rb_wr_en;
wire				rb_rd_en;
wire				rb_buf_empty;
wire				rb_buf_full;
wire [`BUF_WIDTH :0] rb_fifo_counter;
//write_buffer
wire	[31:0]		wb_buf_in;
wire	[31:0]		wb_buf_out;
wire				wb_wr_en;
wire				wb_rd_en;
wire				wb_buf_empty;
wire				wb_buf_full;
wire [`BUF_WIDTH :0] wb_fifo_counter;

reg	[31:0]	wb_buf_in_reg;
reg	[31:0]	wb_buf_out_reg;
reg				wb_wr_en_reg;
reg				wb_rd_en_reg;

assign wb_buf_in = wb_buf_in_reg;
assign wb_buf_out = wb_buf_out_reg;
assign wb_wr_en = wb_wr_en_reg;
assign wb_rd_en = wb_rd_en_reg;
//uart
reg				uart_read_en;
reg	[7:0]		uart_read_data;
reg				uart_data_ready;
reg	[7:0]		uart_write_data;
reg				uart_write_en;
reg				uart_tx_ready;

	uart c_uart(
		.clk(clk),
		.rstn(rst),
		.rx(rx),
		.read_en(uart_read_en),
		.read_data(uart_read_data),
		.data_ready(uart_data_ready),
		.write_data(uart_write_data),
		.write_en(uart_write_en),
		.tx(tx),
		.tx_ready(uart_tx_ready)
	);

	fifo read_buffer(
		.clk(clk),
		.rst(rst),
		.buf_in(rb_buf_in),
		.buf_out(rb_buf_out),
		.wr_en(rb_wr_en),
		.rd_en(rb_rd_en),
		.buf_empty(rb_buf_empty),
		.buf_full(rb_buf_full),
		.fifo_counter(rb_fifo_counter)
	);
	
	fifo write_buffer(
		.clk(clk),
		.rst(rst),
		.buf_in(wb_buf_in),
		.buf_out(wb_buf_out),
		.wr_en(wb_wr_en),
		.rd_en(wb_rd_en),
		.buf_empty(wb_buf_empty),
		.buf_full(wb_buf_full),
		.fifo_counter(wb_fifo_counter)
	);
	
//localparam
	//UART_CTRL			= 0,


always @(posedge clk or negedge rst)
	begin
		if (~rst)
			begin
				//TODO
			end
		else
			begin
				//TODO
			end
	end
	
//From CPU	
always @(*)
begin
	if(w_en)
	begin
		if(!wb_buf_full)
		begin
			wb_buf_in_reg = w_data;
			wb_wr_en_reg = 1;
            //@(posedge clk);
            //#1 wb_wr_en_reg = 0;
		end
	end
	else
	begin
		wb_wr_en_reg = 0;
	end
end

endmodule