2 /mips_system |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|mips_system.v/ioctrl_inst - ioctrl_wb /mips_system |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|mips_system.v/memory_inst - bus_control /mips_system |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|mips_system.v/pipeline_inst - pipeline /mips_system |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|mips_system.v/ram_inst - data_ram_wb mips_system (/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/mips_system.v) 0 0 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000016c000000020000000000000000000000000200000064ffffffff0000008100000003000000020000016c0000000100000003000000000000000100000003 true mips_system (/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/mips_system.v) 1 Design Utilities 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000177000000010000000100000000000000000000000064ffffffff000000810000000000000001000001770000000100000000 false 1 0 0 000000ff00000000000000010000000000000000010000000000000000000000000000000000000277000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004f00000001000000000000002900000001000000000000008400000001000000000000017b0000000100000000 false alu.v 1 work 0 0 000000ff00000000000000010000000000000000010000000000000000000000000000000000000125000000010001000100000000000000000000000064ffffffff000000810000000000000001000001250000000100000000 false work 1 Configure Target Device Design Utilities Implement Design Synthesize - XST User Constraints 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000177000000010000000100000000000000000000000064ffffffff000000810000000000000001000001770000000100000000 false 2 /testbench |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|testbench.v/uut - mips_system/ioctrl_inst - ioctrl_wb/uart_uut - uart_ctl/rx_ctl - rx_ctl /testbench |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|testbench.v/uut - mips_system/memory_inst - bus_control /testbench |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|testbench.v/uut - mips_system/pipeline_inst - pipeline /testbench |home|maar|Code|Git|Verilog|MIPS-UART-module|src|hdl|testbench.v/uut - mips_system/ram_inst - data_ram_wb testbench (/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/testbench.v) 0 0 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000180000000020000000000000000000000000200000064ffffffff000000810000000300000002000001800000000100000003000000000000000100000003 false testbench (/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/testbench.v) 1 Design Utilities 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000177000000010000000100000000000000000000000064ffffffff000000810000000000000001000001770000000100000000 false 1 Simulate Behavioral Model 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000177000000010000000100000000000000000000000064ffffffff000000810000000000000001000001770000000100000000 false Simulate Behavioral Model 000000ff0000000000000002000001510000012001000000060100000002 Behavioral Simulation