ISim log file
Running: /home/maar/Code/Git/Verilog/MIPS-UART-module/project/mipsart/testbench_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/maar/Code/Git/Verilog/MIPS-UART-module/project/mipsart/testbench_isim_beh.wdb 
ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# run 10.00ms
# restart
# run 10.00ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# run 30.00ms
Stopped at time : 33368430 ns : File "/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/if_stage.v" Line 35
# exit 0