/**********************************************************************/ /* ____ ____ */ /* / /\/ / */ /* /___/ \ / */ /* \ \ \/ */ /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ /* / / All Right Reserved. */ /* /---/ /\ */ /* \ \ / \ */ /* \___\/\___\ */ /***********************************************************************/ /* This file is designed for use with ISim build 0xfbc00daa */ #define XSI_HIDE_SYMBOL_SPEC true #include "xsi.h" #include #ifdef __GNUC__ #include #else #include #define alloca _alloca #endif static const char *ng0 = "/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/mips_system.v"; static int ng1[] = {0, 0}; static void NetDecl_71_0(char *t0) { char *t1; char *t2; char *t3; char *t4; char *t5; char *t6; char *t7; unsigned int t8; unsigned int t9; char *t10; unsigned int t11; unsigned int t12; char *t13; unsigned int t14; unsigned int t15; LAB0: t1 = (t0 + 10536U); t2 = *((char **)t1); if (t2 == 0) goto LAB2; LAB3: goto *t2; LAB2: xsi_set_current_line(71, ng0); t2 = ((char*)((ng1))); t3 = (t0 + 10920); t4 = (t3 + 56U); t5 = *((char **)t4); t6 = (t5 + 56U); t7 = *((char **)t6); memset(t7, 0, 8); t8 = 7U; t9 = t8; t10 = (t2 + 4); t11 = *((unsigned int *)t2); t8 = (t8 & t11); t12 = *((unsigned int *)t10); t9 = (t9 & t12); t13 = (t7 + 4); t14 = *((unsigned int *)t7); *((unsigned int *)t7) = (t14 | t8); t15 = *((unsigned int *)t13); *((unsigned int *)t13) = (t15 | t9); xsi_driver_vfirst_trans(t3, 0, 2U); LAB1: return; } extern void work_m_01545345819257358593_3942453009_init() { static char *pe[] = {(void *)NetDecl_71_0}; xsi_register_didat("work_m_01545345819257358593_3942453009", "isim/testbench_isim_beh.exe.sim/work/m_01545345819257358593_3942453009.didat"); xsi_register_executes(pe); }