AYXx X  ,Lt0 0 h$l   $wM MDVZ^ky        " %" %&'*-.00 91B C*D4E>F+U7/@dAaPd_`dmd }d!d"d# #d) 'd+       @@2@@2@@2@@2@@2 HOY aHM HOY 7#0123459:;<=>BCDEFUVWXYZ[\]_`abcdefgv*S/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/ex_stage.vex_stageex_stageclkrstwb_reg_writewb_mem_to_regmem_readmem_writeex_imm_commandex_alu_src_bex_dst_reg_selex_alu_oppstop_iABsign_extend_offsetrtrdopcoders_fwd_selrt_fwd_selmem_fwd_valwb_fwd_valex_dst_regex_opcodeEX_MEM_alu_resultEX_MEM_B_valueEX_MEM_dst_regEX_MEM_opcodeEX_MEM_mem_readEX_MEM_mem_writeEX_MEM_wb_reg_writeEX_MEM_wb_mem_to_regfunc_fieldfunc_codealu_ctlalu_a_inalu_b_inb_valuealu_resultzeroAlways_48_0Always_57_1Cont_66_2Cont_67_3Cont_68_4Cont_69_5Cont_70_6alu_opfunc_codealu_ctlm_05734343435962437432_1098446607aluctl_instwork_m_05734343435962437432_1098446607alu_ctla_inb_inresultzero_flagm_05774762672483521687_2725559894alu_instwork_m_05774762672483521687_2725559894Always_85_7/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/ex_stage.visim/testbench_isim_beh.exe.sim/work/m_05866425861820687629_1844442480.didat