к └√╟AYXДДРРрРИ d ╕ ▄ x╕ H А HxР─╪ф,8Дд┤||$ММььh╪d( PX╘▄Д┤╘╘╘╘╘╘╘Х ] M      Dў Ї ∙     июB№         V    №    Z    №    ^    №    m    №     v         А         И    "    Т    "     Щ         д         о         э                       !    "    '#    1%4    =/5    I96║└>b╠pBb▐    `Dbх     Eb                                                                                 @@     @@2    @@2    @@2U!"#%&()*+/012349:;<>?@Av*S/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/if_stage.vif_stageif_stageclkrstif_id_write_enpc_writepc_sourcepstop_ii_read_eni_addri_instr_injump_addrbranch_addrIF_ID_next_i_addrIF_ID_instructionpc_regpc_nextnext_i_addrLWSWmem_opNetDecl_30_0Cont_33_1Cont_34_2Cont_35_3Always_37_4Always_47_5Always_57_6/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/if_stage.v#+isim/testbench_isim_beh.exe.sim/work/m_12792418291712187595_0228657068.didat