к └√╟AYX╥ДДРРрР░ Ї М ░ ╘ ШH М ╝ Д ┤ ╠  @ht└ р Ё LLLTааHXии°°h╪а № М Ф └ЁLLLд MO      Eў Ї     Y    №    ]    №    a    №    j    №    t                  Б         Й          Ц          д         №    "         "         "        "    %         /    9     C!    M"    W)4м░жa╗╨зa╠╨кa▐амaэpоa                                             @@2     @@2     @@2    @@2c !")*+,-./0345678v*S/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/mem_stage.vmem_stagemem_stageclkrstmem_readmem_writealu_resultBdst_regwb_reg_writewb_mem_to_regpstop_iMEM_WB_dst_regMEM_WB_reg_writeMEM_WB_mem_to_regMEM_WB_mem_outMEM_WB_alu_outd_read_end_write_end_addrd_write_datad_data_inCont_31_0Cont_32_1Cont_33_2Cont_34_3Always_41_4/home/maar/Code/Git/Verilog/MIPS-UART-module/src/hdl/mem_stage.visim/testbench_isim_beh.exe.sim/work/m_16245461553792118434_2321779972.didat