verilog work "../../src/hdl/uart/tx.v"
verilog work "../../src/hdl/uart/rx.v"
verilog work "../../src/hdl/uart/fifo.v"
verilog work "../../src/hdl/uart/tx_ctl.v"
verilog work "../../src/hdl/uart/rx_ctl.v"
verilog work "../../src/hdl/uart/baud_gen.v"
verilog work "../../src/hdl/regfile.v"
verilog work "../../src/hdl/control.v"
verilog work "../../src/hdl/alu_ctrl.v"
verilog work "../../src/hdl/alu.v"
verilog work "../../src/hdl/wb_stage.v"
verilog work "../../src/hdl/uart/uart_ctl.v"
verilog work "../../src/hdl/ram_wb/wb_ram_sc_sw.v"
verilog work "../../src/hdl/mem_stage.v"
verilog work "../../src/hdl/master_wb.v"
verilog work "../../src/hdl/if_stage.v"
verilog work "../../src/hdl/id_stage.v"
verilog work "../../src/hdl/hazard_unit.v"
verilog work "../../src/hdl/forwarding_unit.v"
verilog work "../../src/hdl/ex_stage.v"
vhdl work "../../src/hdl/wb/wb.vhd"
verilog work "../../src/hdl/ram_wb/ram_wb.v"
verilog work "../../src/hdl/pipeline.v"
verilog work "../../src/hdl/ioctrl_wb.v"
verilog work "../../src/hdl/gpio_wb.v"
verilog work "../../src/hdl/dp_memory.v"
verilog work "../../src/hdl/mips_system.v"
verilog work "../../src/hdl/testbench.v"
verilog work "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"